NTSC Timing Synthesis
Rich Lewis - KE5HHU
12/30/2007
The NTSC video specification defines Color Burst Frequency as 3.579545 MHz. This is the highest frequency encountered in the system.
The Horizontal Scanning Frequency shall be 2/455 of the Color Burst Frequency. This equals 15.73426 KHz, or 63.56 uS.
The Vertical Scanning Frequency shall be an interlaced 525 horizontal scans. This equals 29.97 Hz or 33.367 mS.
In designing a signal synthesizer to encode the RF signal into the NTSC data stream a base frequency of 14.31818 MHz is chosen. This is four times the Color Burst Frequency. This gives me a clock period of 69.84 nS. 910 clock periods gives me the horizontal period. 455 clock periods gives me 2X the horizontal frequency. This is required in order to correctly transition between scan fields. The 2 interlaced field are 262.5 scans apart from each other. They transition on a halfway point within a horizontal period. This point is missed by nearly every scan converter made.
All of the signals required can be derived from the base clock period and a relationship to the horizontal sync.
| Specification |
Minimum |
Design |
Maximum |
| Horizontal Period 2/455 of Color Burst | 63.56 µS | ||
| Horizontal Blanking - 157 clocks | 10.49 µS | 10.965 µS | 11.44 µS |
| Horizontal Sync - 72 clocks | 4.45 µS | 5.0286 µS | 5.08 µS |
| Front Porch - 21 clocks | > 1.27 µS | 1.467 µS | |
| Breezeway - 6 clocks | > .381 µS | .419 µS | |
| Burst - 9 cycles - 36 clocks | 2.514 µS | ||
| Equalizing Pulses - 32 clocks | 2.0 µS | 2.235 µS | 2.54 µS |
| Serration Pulses - 64 clocks | 3.8 µS | 4.469 µS | 5.1 µS |
| Vertical Blanking - 21 lines | 1.17 mS | 1.33467 mS | 1.33 mS |
| Vertical Sync - 3 lines | 190.67 µS |
The horizontal blanking period is comprised of:
FPorch + HSync + Breezeway + Burst + other = HBlank
21 + 72 + 6 +36 +22 = 157
The horizontal period is:
HBlank + HActive = HScan
157 + 753 = 910
State Machines
My frame buffer designs in the Eighties used 2 sets of ROMS, one with an output register and the other with a counter on the output. The first ROM held the states, and the second ROM held the periods. A set of these existed for each of the horizontal and vertical control circuits. Fast TTL but high part count. At the time few ROMs existed that were fast enough, i.e. better than 70 nS.
Another method is to have the current ROM state determine the next address for the ROM, or the next state. This type of feed back is useful for looping circuits such as this. The signal states must occur at regular intervals with out fail. The only external stimuli that may affect the loop would be an master sync input that would synchronize all of the equipment to a common vertical sync period. The problem with the horizontal timing is that several actions must occur within a short time period, and a few actions occurring on long time periods. This is why 910 states are required, each state exists for 1 clock. A 10 bit counter will be required to track the 910 possible states. The final state, #910 must reset the state machine back to state #1. The ROM must be at least 1K in size and be able to change states in a 70 nS period. The vertical timing would need to have 525 states, so again, a 1K ROM that can change states with 70 nS.
I need several horizontal timing signals, 2xHSync, HSync, HBlank, and Burst, so my ROM must be 4 bits deep. 8 bits are probably better.